module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 

    parameter IDLE = 4'd0;
    parameter FOUT = 4'd1;
    parameter D0 = 4'd2;
    parameter D1 = 4'd3;
    parameter D2 = 4'd4;
    parameter D3 = 4'd5;
    parameter D4 = 4'd6;
    parameter FONE = 4'd7;
    parameter FZERO = 4'd8;
    
    reg	[3:0]	state;
    reg	[3:0]	next_state;
    
    always @(posedge clk)
        begin
            if(!resetn)
                begin
                	state <= IDLE;
                end
            else
                begin
                    state <= next_state;
                end
        end
    
    always @(*)
        begin
            case(state)
                IDLE:	next_state = FOUT;
                FOUT:	next_state = D0;
                D0:		next_state = x ? D1 : D0;
                D1:		next_state = x ? D1 : D2;
                D2:		next_state = x ? D3 : D0;
                D3:		next_state = y ? FONE : D4;
                D4:		next_state = y ? FONE : FZERO;
                FONE:	next_state = FONE;
                FZERO:	next_state = FZERO;
                default:next_state = IDLE;
            endcase
        end
    
    assign f = (state == FOUT);
    assign g = ((state == D3) || (state == D4) || (state == FONE));
    
endmodule
